UVM-Testbench-Example-2

2024-01-24
#UVM #Testbench Structure
UVM

這個例子跟前一個例子的Testbench架構是一樣的

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Design

這個design的input是addr和data，如果addr小於等於 ADDR_DIV 的話，就會把資料導到addr_a/data_a，反之則導到addr_b/data_b。

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module switch
  # (parameter ADDR_WIDTH = 8,
     parameter DATA_WIDTH = 16,
     parameter ADDR_DIV = 8'h3F
    )
  ( input clk,
    input rstn,
    input vld,

    input [ADDR_WIDTH-1:0] addr,
    input [DATA_WIDTH-1:0] data,

    output reg [ADDR_WIDTH-1:0] addr_a,
    output reg [DATA_WIDTH-1:0] data_a,
    output reg [ADDR_WIDTH-1:0] addr_b,
    output reg [DATA_WIDTH-1:0] data_b
  );

  always @ (posedge clk) begin
    if (!rstn) begin
        addr_a <= 0;
        data_a <= 0;
        addr_b <= 0;
        data_b <= 0;
    end
    else begin
      if (vld) begin
        if (addr >= 0 & addr <= ADDR_DIV) begin
            addr_a <= addr;
            data_a <= data;
            addr_b <= 0;
            data_b <= 0;
        end else begin
            addr_a <= 0;
            data_a <= 0;
            addr_b <= addr;
            data_b <= data;
        end
      end
    end
  end
endmodule

Testbench & Interface

這邊就把完整的testbench不分段直接放上，testbench需要注意的地方是monitor使用了兩個thread輪流監聽interface的資料，透過一個semaphore來讓兩個thread輪流去監聽interface。

因為design裡面addr_a/data_a和addr_b/data_b也是要等到下一個clock posedge的時候才會變化，所以monitor在中間插了一個@ (posedge vif.clk)。
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import uvm_pkg::*;
`include "uvm_macros.svh"

interface switch_if (input bit clk);
  logic rstn;
  logic vld;
  logic [7:0] addr;
  logic [15:0] data;
  logic [7:0] addr_a;
  logic [15:0] data_a;
  logic [7:0] addr_b;
  logic [15:0] data_b;
endinterface

class switch_item extends uvm_sequence_item;
    bit [7:0]  addr;
    bit [15:0] data;
    bit [7:0]  addr_a;
    bit [15:0] data_a;
    bit [7:0]  addr_b;
    bit [15:0] data_b;

    `uvm_object_utils_begin(switch_item)
        `uvm_field_int(addr, UVM_DEFAULT)
        `uvm_field_int(data, UVM_DEFAULT)
        `uvm_field_int(addr_a, UVM_DEFAULT)
        `uvm_field_int(data_a, UVM_DEFAULT)
        `uvm_field_int(addr_b, UVM_DEFAULT)
        `uvm_field_int(data_b, UVM_DEFAULT)
    `uvm_object_utils_end

    virtual function string convert2str();
        return $sformatf("addr=0x%0h data=0x%0h addr_a=0x%0h data_a=0x%0h addr_b=0x%0h data_b=0x%0h",
                          addr, data, addr_a, data_a, addr_b, data_b);
    endfunction

    function new(string name = "switch_item");
        super.new(name);
    endfunction
endclass

class driver extends uvm_driver#(switch_item);
    `uvm_component_utils(driver)
    function new(string name = "driver", uvm_component parent = null);
        super.new(name, parent);
    endfunction

    virtual switch_if vif;

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        if(!uvm_config_db#(virtual switch_if)::get(this, "", "switch_if", vif))
            `uvm_fatal("DRV", "Could NOT get vif");
    endfunction

    virtual task run_phase(uvm_phase phase);
        super.run_phase(phase);
        forever begin
            switch_item m_item;
            `uvm_info("DRV", $sformatf("wait for item from sequencer"), UVM_LOW);
            seq_item_port.get_next_item(m_item);
            drive_item(m_item);
            seq_item_port.item_done();
        end
    endtask

    virtual task drive_item(switch_item m_item);
        vif.vld <= 1;
        vif.addr <= m_item.addr;
        vif.data <= m_item.data;
        @(posedge vif.clk);
        // while (!vif.vld) begin
        //     `uvm_info("DRV", "wait until vld is high", UVM_LOW)
        //     @(posedge vif.clk);
        // end

        vif.vld <= 0;
    endtask
endclass

class monitor extends uvm_monitor;
    `uvm_component_utils(monitor)
    function new(string name = "Monitor", uvm_component parent = null);
        super.new(name, parent);
    endfunction

    uvm_analysis_port #(switch_item) mon_analysis_port;
    virtual switch_if vif;
    semaphore sema4;

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        if(!uvm_config_db#(virtual switch_if)::get(this, "", "switch_if", vif)) begin
          `uvm_fatal("MON", "Could not get vif");
        end
        else begin
            `uvm_info("MON", "Could get vif", UVM_LOW);
        end
        sema4 = new(1);
        mon_analysis_port = new("mon_analysis_port", this);
    endfunction

    // virtual task run_phase(uvm_phase phase);
    //     super.run_phase(phase);

    //     forever begin
    //       @ (posedge vif.clk);
    //       if (vif.vld) begin
    //         switch_item item = new;
    //         item.addr = vif.addr;
    //         item.data = vif.data;

    //         @ (posedge vif.clk);
    //         item.addr_a = vif.addr_a;
    //         item.data_a = vif.data_a;
    //         item.addr_b = vif.addr_b;
    //         item.data_b = vif.data_b;

    //         `uvm_info(get_type_name(), $sformatf("Monitor found packet %s", item.convert2str()), UVM_LOW)
    //         mon_analysis_port.write(item);
    //       end
    //     end
    // endtask

    virtual task run_phase(uvm_phase phase);
      super.run_phase(phase);

      fork
        sample_port("Thread1");
        sample_port("Thread2");
      join
    endtask

    virtual task sample_port(string tag);
      `uvm_info("MON", $sformatf("thread:%s start", tag), UVM_LOW)
      forever begin
        @ (posedge vif.clk);
        if (vif.vld) begin
          switch_item item = new;
          sema4.get();
          item.addr = vif.addr;
          item.data = vif.data;
          `uvm_info("MON", $sformatf("%s 1st step", tag), UVM_LOW)
          @ (posedge vif.clk);
          item.addr_a = vif.addr_a;
          item.data_a = vif.data_a;
          item.addr_b = vif.addr_b;
          item.data_b = vif.data_b;
          `uvm_info("MON", $sformatf("%s 2nd step", tag), UVM_LOW)
          mon_analysis_port.write(item);
          sema4.put();
        end
      end
    endtask
endclass

class agent extends uvm_agent;
  `uvm_component_utils(agent)
  function new(string name = "agent", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  monitor m0;
  driver d0;
  uvm_sequencer #(switch_item) s0;

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    m0 = monitor::type_id::create("m0", this);
    d0 = driver::type_id::create("d0", this);
    s0 = uvm_sequencer#(switch_item)::type_id::create("s0", this);
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    d0.seq_item_port.connect(s0.seq_item_export);
  endfunction
endclass

class scoreboard extends uvm_scoreboard;
  `uvm_component_utils(scoreboard)
  function new(string name = "scoreboard", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  // switch_item refq[`DEPTH];
  uvm_analysis_imp #(switch_item, scoreboard) m_analysis_imp;

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    m_analysis_imp = new("m_analysis_imp", this);
  endfunction

  virtual function write(switch_item item);
    // if(!item.rstn) begin
    //   if (item.addr_a == 0 && item.data_a != 0 && item.addr_b != 0 && item.data_b != 0) begin
    //     `uvm_info(get_type_name(), $sformatf("rst addr_a data_a addr_b data_b are all zero"), UVM_LOW);
    //   end
    //   else begin
    //     `uvm_error(get_type_name(),
    //               $sformatf("In rst state. but not all data are zero addr_a=0x%0h data_a=0x%0h addr_b=0x%0h addr_b=0x%0h",
    //               item.addr_a, item.data_a, item.addr_b, item.data_b)
    //               );
    //   end
    // end
    // else begin
      if (item.addr <= 8'h3F) begin
        if (item.addr == item.addr_a && item.data == item.data_a && 0 == item.addr_b && 0 == item.data_b) begin
          `uvm_info(get_type_name(), $sformatf("item.addr <= ADDR_DIV expected result"), UVM_LOW);
        end
        else begin
          `uvm_error(get_type_name(),
                    $sformatf("item.addr <= ADDR_DIV result error addr=0x%0h data=0x%0h addr_a=0x%0h data_a=0x%0h addr_b=0x%0h addr_b=0x%0h",
                    item.addr, item.data, item.addr_a, item.data_a, item.addr_b, item.data_b)
                    );
        end
      end
      else begin
        if (item.addr == item.addr_b && item.data == item.data_b && 0 == item.addr_a && 0 == item.data_a) begin
          `uvm_info(get_type_name(), $sformatf("item.addr > ADDR_DIV expected result"), UVM_LOW);
        end
        else begin
          `uvm_error(get_type_name(),
                     $sformatf("item.addr > ADDR_DIV result error addr=0x%0h data=0x%0h addr_a=0x%0h data_a=0x%0h addr_b=0x%0h addr_b=0x%0h",
                     item.addr, item.data, item.addr_a, item.data_a, item.addr_b, item.data_b)
                    );
        end
      end
    // end
  endfunction
endclass

class env extends uvm_env;
  `uvm_component_utils(env)
  function new(string name = "env", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  agent a0;
  scoreboard sb0;

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    a0 = agent::type_id::create("a0", this);
    sb0 = scoreboard::type_id::create("sb0", this);
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    a0.m0.mon_analysis_port.connect(sb0.m_analysis_imp);
  endfunction
endclass

class gen_item_seq extends uvm_sequence;
  `uvm_object_utils(gen_item_seq)
  function new(string name = "gen_item_seq");
    super.new(name);
  endfunction

  int num = 10;

  virtual task body();
    for (int i = 0; i < num; i++) begin
      switch_item m_item = switch_item::type_id::create("m_item");
      start_item(m_item);
      m_item.addr = (i + 8'h38);
      m_item.data = $random;
      `uvm_info("SEQ", $sformatf("Generate1 new item: "), UVM_LOW)
      m_item.print();
      finish_item(m_item);
    end

    `uvm_info("SEQ", $sformatf("done %0d time", num), UVM_LOW)
  endtask
endclass

class test extends uvm_test;
  `uvm_component_utils(test)
  function new(string name = "test", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  env e0;
  virtual switch_if vif;

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    e0 = env::type_id::create("e0", this);
    if (!uvm_config_db#(virtual switch_if)::get(this, "", "switch_if", vif))
      `uvm_fatal("TEST", "Did not get vif")

    uvm_config_db#(virtual switch_if)::set(this, "e0.a0.*", "switch_if", vif);
  endfunction

  virtual function void end_of_elaboration_phase(uvm_phase phase);
    super.end_of_elaboration_phase(phase);
    uvm_top.print_topology();
  endfunction

  virtual task run_phase(uvm_phase phase);
    gen_item_seq seq = gen_item_seq::type_id::create("seq");
    phase.raise_objection(this);

    apply_reset();
    seq.num = 25;
    $display("seq.start");
    seq.start(e0.a0.s0);
    $display("seq gogo");
    #1000
    phase.drop_objection(this);
  endtask

  virtual task apply_reset();
    vif.rstn <= 0;
    $display("apply_reset vif.rstn:%0b", vif.rstn);
    repeat(5) @(posedge vif.clk);
    $display("apply_reset vif.rstn:%0b", vif.rstn);
    vif.rstn <= 1;
    repeat(10) @(posedge vif.clk);
    $display("apply_reset vif.rstn:%0b", vif.rstn);
  endtask
endclass

module tb;
    reg clk = 0;
    always #10 clk = ~clk;
    switch_if _if(clk);

    switch u0(.clk(clk),
              .rstn(_if.rstn),
              .vld(_if.vld),
              .addr(_if.addr),
              .data(_if.data),
              .addr_a(_if.addr_a),
              .data_a(_if.data_a),
              .addr_b(_if.addr_b),
              .data_b(_if.data_b)
               );
    initial begin
        $display("tb_start");
        uvm_config_db #(virtual switch_if)::set (null, "uvm_test_top", "switch_if", _if);
        run_test("test");
        $display("tb_end");
    end

    initial begin
      $dumpvars;
      $dumpfile("dump.vcd");
    end
endmodule

Output

我的code裡面addr是從0x38開始直接往下加，data才是用random的，比較容易看結果是不是正確的。

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Reading pref.tcl

# 2021.2

# vsim -c tb -do "run 10000"
# Start time: 00:13:16 on Jan 25,2024
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: .\tb.sv(243): (vopt-2250) Function "write" has no return value assignment.
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
# //  Questa Intel Starter FPGA Edition-64
# //  Version 2021.2 win64 Apr 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading mtiUvm.uvm_pkg(fast)
# Loading work.tb_sv_unit(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# Loading work.tb(fast)
# Loading work.switch_if(fast)
# ** Warning: (vsim-3764) Stand-alone call to function 'write' treated as implicit void cast.
#    Time: 0 ns  Iteration: 0  Region: /uvm_pkg::uvm_analysis_imp #(tb_sv_unit::switch_item, tb_sv_unit::scoreboard) File: C:/intelFPGA/22.1std/questa_fse/win64/../verilog_src/uvm-1.1d/src/tlm1/uvm_analysis_port.svh Line:
114
# Loading C:/intelFPGA/22.1std/questa_fse/uvm-1.1d\win64\uvm_dpi.dll
# run 10000
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
#   ***********       IMPORTANT RELEASE NOTES         ************
#
#   You are using a version of the UVM library that has been compiled
#   with `UVM_NO_DEPRECATED undefined.
#   See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
#   You are using a version of the UVM library that has been compiled
#   with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
#   See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
#       (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# tb_start
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# ** Warning: (vsim-PLI-3826) $dumpfile : This task should be called prior to the $dumpvars
# task.  The $dumpfile task will be ignored.
#    Time: 0 ns  Iteration: 0  Process: /tb/#INITIAL#395 File: ./tb.sv Line: 397
# UVM_INFO .\tb.sv(146) @ 0: uvm_test_top.e0.a0.m0 [MON] Could get vif
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# --------------------------------------------------------------
# Name                       Type                    Size  Value
# --------------------------------------------------------------
# uvm_test_top               test                    -     @471
#   e0                       env                     -     @478
#     a0                     agent                   -     @488
#       d0                   driver                  -     @510
#         rsp_port           uvm_analysis_port       -     @525
#         seq_item_port      uvm_seq_item_pull_port  -     @517
#       m0                   monitor                 -     @503
#         mon_analysis_port  uvm_analysis_port       -     @644
#       s0                   uvm_sequencer           -     @533
#         rsp_export         uvm_analysis_export     -     @540
#         seq_item_export    uvm_seq_item_pull_imp   -     @634
#         arbitration_queue  array                   0     -
#         lock_queue         array                   0     -
#         num_last_reqs      integral                32    'd1
#         num_last_rsps      integral                32    'd1
#     sb0                    scoreboard              -     @495
#       m_analysis_imp       uvm_analysis_imp        -     @657
# --------------------------------------------------------------
#
# apply_reset vif.rstn:x
# UVM_INFO .\tb.sv(184) @ 0: uvm_test_top.e0.a0.m0 [MON] thread:Thread1 start
# UVM_INFO .\tb.sv(184) @ 0: uvm_test_top.e0.a0.m0 [MON] thread:Thread2 start
# UVM_INFO .\tb.sv(108) @ 0: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# apply_reset vif.rstn:0
# apply_reset vif.rstn:1
# seq.start
# UVM_INFO .\tb.sv(317) @ 290: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @696
#   addr                         integral     8     'h38
#   data                         integral     16    'h3524
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    290
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 310: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(192) @ 310: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 310: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @709
#   addr                         integral     8     'h39
#   data                         integral     16    'h5e81
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    310
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 330: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 330: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(258) @ 330: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 330: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 330: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @713
#   addr                         integral     8     'h3a
#   data                         integral     16    'hd609
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    330
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 350: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 350: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(258) @ 350: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 350: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 350: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @721
#   addr                         integral     8     'h3b
#   data                         integral     16    'h5663
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    350
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 370: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 370: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(258) @ 370: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 370: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 370: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @729
#   addr                         integral     8     'h3c
#   data                         integral     16    'h7b0d
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    370
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 390: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 390: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(258) @ 390: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 390: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 390: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @737
#   addr                         integral     8     'h3d
#   data                         integral     16    'h998d
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    390
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 410: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 410: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(258) @ 410: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 410: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 410: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @745
#   addr                         integral     8     'h3e
#   data                         integral     16    'h8465
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    410
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 430: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 430: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(258) @ 430: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 430: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 430: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @753
#   addr                         integral     8     'h3f
#   data                         integral     16    'h5212
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    430
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 450: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 450: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(258) @ 450: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 450: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 450: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @761
#   addr                         integral     8     'h40
#   data                         integral     16    'he301
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    450
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 470: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 470: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(258) @ 470: uvm_test_top.e0.sb0 [scoreboard] item.addr <= ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 470: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 470: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @769
#   addr                         integral     8     'h41
#   data                         integral     16    'hcd0d
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    470
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 490: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 490: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 490: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 490: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 490: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @777
#   addr                         integral     8     'h42
#   data                         integral     16    'hf176
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    490
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 510: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 510: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 510: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 510: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 510: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @785
#   addr                         integral     8     'h43
#   data                         integral     16    'hcd3d
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    510
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 530: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 530: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 530: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 530: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 530: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @793
#   addr                         integral     8     'h44
#   data                         integral     16    'h57ed
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    530
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 550: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 550: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 550: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 550: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 550: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @801
#   addr                         integral     8     'h45
#   data                         integral     16    'hf78c
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    550
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 570: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 570: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 570: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 570: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 570: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @809
#   addr                         integral     8     'h46
#   data                         integral     16    'he9f9
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    570
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 590: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 590: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 590: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 590: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 590: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @817
#   addr                         integral     8     'h47
#   data                         integral     16    'h24c6
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    590
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 610: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 610: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 610: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 610: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 610: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @825
#   addr                         integral     8     'h48
#   data                         integral     16    'h84c5
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    610
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 630: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 630: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 630: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 630: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 630: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @833
#   addr                         integral     8     'h49
#   data                         integral     16    'hd2aa
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    630
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 650: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 650: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 650: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 650: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 650: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @841
#   addr                         integral     8     'h4a
#   data                         integral     16    'hf7e5
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    650
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 670: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 670: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 670: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 670: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 670: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @849
#   addr                         integral     8     'h4b
#   data                         integral     16    'h7277
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    670
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 690: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 690: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 690: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 690: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 690: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @857
#   addr                         integral     8     'h4c
#   data                         integral     16    'hd612
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    690
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 710: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 710: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 710: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 710: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 710: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @865
#   addr                         integral     8     'h4d
#   data                         integral     16    'hdb8f
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    710
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 730: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 730: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 730: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 730: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 730: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @873
#   addr                         integral     8     'h4e
#   data                         integral     16    'h69f2
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    730
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 750: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 750: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 750: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 750: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(317) @ 750: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @881
#   addr                         integral     8     'h4f
#   data                         integral     16    'h96ce
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    750
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 770: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 770: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 770: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 770: uvm_test_top.e0.a0.m0 [MON] Thread2 1st step
# UVM_INFO .\tb.sv(317) @ 770: uvm_test_top.e0.a0.s0@@seq [SEQ] Generate1 new item:
# ---------------------------------------------------------------------------
# Name                           Type         Size  Value
# ---------------------------------------------------------------------------
# m_item                         switch_item  -     @889
#   addr                         integral     8     'h50
#   data                         integral     16    'h7ae8
#   addr_a                       integral     8     'h0
#   data_a                       integral     16    'h0
#   addr_b                       integral     8     'h0
#   data_b                       integral     16    'h0
#   begin_time                   time         64    770
#   depth                        int          32    'd2
#   parent sequence (name)       string       3     seq
#   parent sequence (full name)  string       25    uvm_test_top.e0.a0.s0.seq
#   sequencer                    string       21    uvm_test_top.e0.a0.s0
# ---------------------------------------------------------------------------
# UVM_INFO .\tb.sv(108) @ 790: uvm_test_top.e0.a0.d0 [DRV] wait for item from sequencer
# UVM_INFO .\tb.sv(198) @ 790: uvm_test_top.e0.a0.m0 [MON] Thread2 2nd step
# UVM_INFO .\tb.sv(269) @ 790: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO .\tb.sv(192) @ 790: uvm_test_top.e0.a0.m0 [MON] Thread1 1st step
# UVM_INFO .\tb.sv(322) @ 790: uvm_test_top.e0.a0.s0@@seq [SEQ] done 25 time
# seq gogo
# UVM_INFO .\tb.sv(198) @ 810: uvm_test_top.e0.a0.m0 [MON] Thread1 2nd step
# UVM_INFO .\tb.sv(269) @ 810: uvm_test_top.e0.sb0 [scoreboard] item.addr > ADDR_DIV expected result
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 1790: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO :  135
# UVM_WARNING :    0
# UVM_ERROR :    0
# UVM_FATAL :    0
# ** Report counts by id
# [DRV]    26
# [MON]    53
# [Questa UVM]     2
# [RNTST]     1
# [SEQ]    26
# [TEST_DONE]     1
# [UVMTOP]     1
# [scoreboard]    25
# ** Note: $finish    : C:/intelFPGA/22.1std/questa_fse/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
#    Time: 1790 ns  Iteration: 54  Instance: /tb
# End time: 00:13:20 on Jan 25,2024, Elapsed time: 0:00:04
# Errors: 0, Warnings: 3