1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293
| parameter ADDR_WIDTH = 8; parameter DATA_WIDTH = 16; parameter ADDR_DIV = 8'h3F;
module switch ( input clk, input rstn, input vld,
input [ADDR_WIDTH-1:0] addr, input [DATA_WIDTH-1:0] data,
output reg [ADDR_WIDTH-1:0] addr_a, output reg [DATA_WIDTH-1:0] data_a,
output reg [ADDR_WIDTH-1:0] addr_b, output reg [DATA_WIDTH-1:0] data_b );
always @ (posedge clk) begin if (!rstn) begin addr_a <= 0; data_a <= 0; addr_b <= 0; data_b <= 0; end else begin if (vld) begin if (addr >= 0 & addr <= ADDR_DIV) begin addr_a <= addr; data_a <= data; addr_b <= 0; data_b <= 0; $display ("1[design] T:%0t addr:0x%0h data:0x%0h addr_a:0x%0h data_a:0x%0h addr_b:0x%0h data_b:0x%0h", $time, addr, data, addr_a, data_a, addr_b, data_b); end else begin addr_a <= 0; data_a <= 0; addr_b <= addr; data_b <= data; $display ("2[design] T:%0t addr:0x%0h data:0x%0h addr_a:0x%0h data_a:0x%0h addr_b:0x%0h data_b:0x%0h", $time, addr, data, addr_a, data_a, addr_b, data_b); end end end end endmodule
class switch_item; bit[ADDR_WIDTH-1:0] addr; bit[DATA_WIDTH-1:0] data;
bit [ADDR_WIDTH-1:0] addr_a; bit [DATA_WIDTH-1:0] data_a; bit [ADDR_WIDTH-1:0] addr_b; bit [DATA_WIDTH-1:0] data_b;
function void rand_val(); this.addr = $urandom_range(0, (2**ADDR_WIDTH)-1); this.addr = (this.addr/8)*8; this.data = $urandom_range(0, (2**DATA_WIDTH)-1); endfunction
function void display_val(string tag = ""); $display ("[transaction] T:%0t %s addr:0x%0h data:0x%0h addr_a:0x%0h data_a:0x%0h addr_b:0x%0h data_b:0x%0h", $time, tag, addr, data, addr_a, data_a, addr_b, data_b); endfunction endclass
interface switch_if(input bit clk); logic rstn; logic vld;
logic [ADDR_WIDTH-1:0] addr; logic [DATA_WIDTH-1:0] data;
logic [ADDR_WIDTH-1:0] addr_a; logic [DATA_WIDTH-1:0] data_a;
logic [ADDR_WIDTH-1:0] addr_b; logic [DATA_WIDTH-1:0] data_b; endinterface
class generator; mailbox mbx; event drv_event; function new(mailbox mbx, event drv_event); this.mbx = mbx; this.drv_event = drv_event; endfunction
task run(); $display("generator running"); for (int i = 0; i < 20; i++) begin switch_item item = new(); item.rand_val(); item.display_val(); mbx.put(item); @(drv_event); end
$display("generator done"); endtask endclass
class driver; mailbox mbx; event drv_event; virtual switch_if vif;
function new(mailbox mbx, event drv_event); this.mbx = mbx; this.drv_event = drv_event; endfunction
task run(); $display("driver running");
$display("drv detect clk rising"); forever begin switch_item item; @(posedge vif.clk); mbx.get(item); item.display_val("driver"); vif.addr <= item.addr; vif.data <= item.data; vif.vld <= 1; $display("t:%0t drv detect clk rising", $time()); ->drv_event;
#1 vif.vld <= 0;
#1 vif.vld <= 1; end endtask endclass
class scoreboard; mailbox mbx; function new(mailbox mbx); this.mbx = mbx; endfunction
task run(); $display("scoreboard running"); forever begin switch_item item; mbx.get(item);
if (item.addr inside {[0:'h3f]}) begin if (item.addr_a != item.addr | item.data_a != item.data) $display ("T:%0t [scoreboard] ERROR addr:0x%0h data:0x%0h addr_a:0x%0h data_a:0x%0h", $time, item.addr, item.data, item.addr_a, item.data_a); else $display ("T:%0t [scoreboard] PASS addr:0x%0h data:0x%0h addr_a:0x%0h data_a:0x%0h", $time, item.addr, item.data, item.addr_a, item.data_a); end else begin if (item.addr_b != item.addr | item.data_b != item.data) $display ("T:%0t [scoreboard] ERROR addr:0x%0h data:0x%0h addr_b:0x%0h data_b:0x%0h", $time, item.addr, item.data, item.addr_b, item.data_b); else $display ("T:%0t [scoreboard] PASS addr:0x%0h data:0x%0h addr_b:0x%0h data_b:0x%0h", $time, item.addr, item.data, item.addr_b, item.data_b); end end endtask endclass
class monitor; mailbox mbx; virtual switch_if vif; semaphore sema4;
function new(mailbox mbx); this.mbx = mbx; sema4 = new(1); endfunction
task run(); $display("t:%0t monitor running", $time); forever begin switch_item item; @(posedge vif.clk); if (vif.clk && vif.vld) begin item = new(); item.addr = vif.addr; item.data = vif.data;
@(posedge vif.clk); item.addr_a = vif.addr_a; item.data_a = vif.data_a; item.addr_b = vif.addr_b; item.data_b = vif.data_b; mbx.put(item); $display ("T=%0t monitor put data to scoreboard", $time); end end endtask endclass
class environment;
driver driver0; generator generator0; event drv_event;
monitor monitor0; scoreboard scoreboard0;
mailbox drv_mbx; mailbox scb_mbx;
virtual switch_if vif;
function new(); drv_mbx = new(); scb_mbx = new();
driver0 = new(drv_mbx, drv_event); generator0 = new(drv_mbx, drv_event);
monitor0 = new(scb_mbx); scoreboard0 = new(scb_mbx); endfunction
task run(); $display("env running"); monitor0.vif = vif; driver0.vif = vif;
fork driver0.run(); generator0.run(); monitor0.run(); scoreboard0.run(); join endtask endclass
class test; environment env0;
function new(); env0 = new(); endfunction
task run(); $display("test running"); env0.run(); endtask endclass
module tb; bit clk; always #10 clk = ~clk;
switch_if if0(clk); switch dut( .clk(if0.clk), .rstn(if0.rstn), .vld(if0.vld), .addr(if0.addr), .data(if0.data), .addr_a(if0.addr_a), .data_a(if0.data_a), .addr_b(if0.addr_b), .data_b(if0.data_b)); test t0;
int i = 0;
switch_item item;
initial begin $display("tb top running"); clk <= 0; if0.rstn <= 1; t0 = new(); t0.env0.vif = if0; t0.run(); #10 if0.rstn <= 1;
$display("tb top finished"); #200 $finish(); end endmodule
|