SystemVerilog - Constraint: disable constraint

2023-07-25
SystemVerilog

Constraint可以用來限制random出來的值,也可以刻意把constraint關掉,解除random的限制,以下為一個簡單的例子。
例子的constraint限制random出來的結果一定會是1,把constraint_mode設定為0之後則可以關閉constraint。

Example:

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class rand_cls;
rand bit[2:0] rand_val;

constraint c_rand_val {rand_val == 1;}
endclass

module tb;
rand_cls rand_pkg;

initial begin
rand_pkg = new();

$display("default constraint_mode:%0d", rand_pkg.c_rand_val.constraint_mode());
for (int i = 0; i < 10; i++) begin
rand_pkg.randomize();
$display("rand_val:%0d", rand_pkg.rand_val);
end

$display("disable constraint mode");
rand_pkg.c_rand_val.constraint_mode(0);
$display("constraint_mode:%0d", rand_pkg.c_rand_val.constraint_mode());

for (int i = 0; i < 10; i++) begin
rand_pkg.randomize();
$display("rand_val:%0d", rand_pkg.rand_val);
end
end
endmodule

Output

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# KERNEL: default constraint_mode:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: rand_val:1
# KERNEL: disable constraint mode
# KERNEL: constraint_mode:0
# KERNEL: rand_val:6
# KERNEL: rand_val:5
# KERNEL: rand_val:3
# KERNEL: rand_val:4
# KERNEL: rand_val:7
# KERNEL: rand_val:5
# KERNEL: rand_val:3
# KERNEL: rand_val:0
# KERNEL: rand_val:7
# KERNEL: rand_val:0

上面的output可以看到在constraint_mode設定為0之後的output的random value就是隨機數了