SystemVerilog的logic和bit資料型態

2023-06-01
#SystemVerilog
SystemVerilog

logic 型態有四種state，zero(0), one(1), unknown(X), high-impedence(Z)
bit 型態有兩種state，zero(0), one(1)

verilog的
reg型態只能在always和initial這兩種block中驅動，而
wire型態只能用assign來驅動

logic

logic example

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module tb();
    logic [7:0] logic_array;
    logic logic_bit1;
    logic logic_bit2;

    assign logic_bit2 = 0;
    assign logic_bit1 = logic_array[0];

    initial begin
        $display("time:%0d logic_array:%0x logic_bit1:%0b logic_bit2:",$time, logic_array, logic_bit1, logic_bit2);
        logic_array = 8'hFF;
        $display("time:%0d logic_array:%0x logic_bit1:%0b logic_bit2:",$time, logic_array, logic_bit1, logic_bit2);
        #1
        $display("time:%0d logic_array:%0x logic_bit1:%0b logic_bit2:",$time, logic_array, logic_bit1, logic_bit2);
        $finish;
    end
endmodule

Output

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# run -all
# time:0 logic_array:x logic_bit1:x logic_bit2:0
# time:0 logic_array:ff logic_bit1:x logic_bit2:0
# time:1 logic_array:ff logic_bit1:1 logic_bit2:0
# ** Note: $finish    : ./logic.sv(15)

bit

在testbench環境中很多狀況我們不需要四種state(0,1,X,Z)的value，像是類似紀錄packet.length通常就是個數值，所以SystemVerilog增加了一些2-state的資料型態，可以更快的simulation。
如果是4-state的資料型態傳換或assign到4-state的資料型態，那unknown(X)或high-impedence(Z) bit就會轉直接轉換成0。

bit example

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module tb();
    bit [7:0] bit_array;
    bit bit_a;
    bit bit_b;

    initial begin
        $display("time:%0d bit_array:%0b bit_a:%0b bit_b:",$time, bit_array, bit_a, bit_b);
        bit_array = 8'hFF;
        bit_a = 1'b0;
        bit_b = 1'b1;
        $display("time:%0d bit_array:%0b bit_a:%0b bit_b:",$time, bit_array, bit_a, bit_b);
        #1
        bit_array = 8'b000100xz;
        $display("time:%0d bit_array:%0b bit_a:%0b bit_b:",$time, bit_array, bit_a, bit_b);
        $finish;
    end
endmodule

Output

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# run -all
# time:0 bit_array:0 bit_a:0 bit_b:0
# time:0 bit_array:11111111 bit_a:0 bit_b:1
# time:1 bit_array:10000 bit_a:0 bit_b:1
# ** Note: $finish    : bit.sv(15)